@Krom

I'd ask him if he is aware of all the product applications POET can address. In his defense, I underestimated the amount of reading he did before replying. Nevertheless, he seems to be stuck on the idea that POET is only for CHFET gates on an optical interconnect - hence his concession that POET could be useful for niche products. I think he believes that POET is for sending data on and off the processor and nothing else. Who knows? Maybe for folks who work in IT this is what the presentation on the website seems to suggest.

A problem I have with his argument is that he picked what is probably the rate-limiting (slowest) component in the average PC and upgraded it to a better one, suggesting that since SSDs are the best way to speed up your computer, upgrading the CPU/GPU isn't going to lead to the multiples that POET is predicting. In other words, it appears he believes that given a choice of upgrading just aspect of today's technology, the HDD --> SDD upgrade would be the best choice.

Here's a few points I'd want him to comment on before furthering the discussion:

• If POET is adopted it will be used in the processor and the SSD (and RAM, and GPU and, and ,and . . .). It's the breadth of POET that is unique.
• POET components can be stacked or connected with optical cables to simplify and even eliminate interconnects that slow down the speed of a common PC.
• Intel, et al. spends billions every year to improved processor speeds. Obviously they expect improved performance.
• Intel, et al. continues to integrate architecture that was formerly connected via busses into their processor. What would happen if POET could integrate everything into their processor? (Literally everything: CPU/GPU/Radio/HDD/RAM/. . .)
• The published whitepaper is only meant to address one product and does not represent the sum of POET 's potential. The optical interconnect was meant to be POET's entry into the marketplace where it could coexist with CMOS-based components before entering other markets. Since then the strategy has been opened up to consider partnerships with commercial giants to rethink the ineffective and money-destroying CMOS shrink proposition.
• The values given in the whitepaper precede today's scaling effort. Perhaps the whitepaper will be revised once the density of the POET chips can be improved by shrinking the transistors below 100nm.

There's probably more to ask, but if he has considered all of this and he still thinks POET's future is not as bright as we think it is I'd like to hear what he has to say.