What the Cnet article highlights is the economics of progress. What POET needs to demonstrate is a future roadmap that is substantially cheaper than going to 14 and 10 nm in silicon.

That POET can be used in existing foundries is a critically important factor in that it reduces the cost of adoption. What is not known to us are the future costs of scaling down POET from 100nm vs current projections in silicon. I just assume that POET must be cheaper given how much larger it is and thus more headroom for "cheaper" reductions in size.

I would love to see a roundtable discussion of these types of issues with Lee and others available on youtube.