So the NR states "Drive for reduction of feature size to 100-nm range". Where are we now with our feature size? I think our transistors are at about 700-nm (.7-um) based on the MD&A. Should this scaling be straightforward? Any technical hurdles foreseen from this? Hopefully the new equipment will assist in this development and of course the POET developmental alliance with access to their technical staff, and foundry resources! Wow. Exciting times.