So I've re-read the term and the construction several times nows. I believe I understand why you are putting so much emphasis on that particular term. The I/O clock is truly independent of the "internal" clock and there isn't a readily predictable phase relationship in a PLL based system until you begin using phase comparators to change the voltage of the "internal" clock.

So, I still think the "Entire" word is more important than the asynchronous definition because it is how the predictability of the phase relationships is "hopefully artificially" generated outside the original idea of tracking the VCRO to the CPU. According to Jim Otteson it is if we patented A, B, and C, and then the Big Companies add D, they still infringe. If the Voltage Controlled Ring Oscillator is considered the "Entire Variable Speed Ring Oscillator System Clock" then we are good. I'm very uncertain on whether that can happen given the "Entire .. " claim construction. PTSC issued an 8k. Aren't 8Ks materially important?