Can you elaborate? The PLL based systems have 1) an external off chip clock sending in a signal, which then 2) enters into the PLL and then 3) a phase detector determines if the Voltage Controlled Ring Oscillator and the external crystal clock frequency are in sync, and if they are not, then 4) the voltage to the voltage controlled ring oscillator is adjusted so the votage controlled ring oscillator runs faster or slower so the VCRO can get back into phase with the external clock, and then 5) the VCRO sends a signal to the CPU, clocking the CPU, 6) the VCRO gets divided back down to go back into the phase detector to repeat.

That is how the PLL system works. Does it infringe on the 336? That is not a question I'm asking you to answer.