1. Microprocessor (50, 310) with a main CPU (70) and the main CPU shows the following: an arithmetic-logical unity (80), the first batch memory (74) with a register (76) for upper positions and a register (78) for the following positions and the registers are connected with each other to deliver input signals to the arithmetic-logical unity (80), and an exit (86) of the arithmetic-logical unity is connected with the register (76) for upper positions, and the register (76) is so connected for upper positions further that it delivers input signals to an internal data bus (90), and the internal data bus (90) is connected bidirectional to a loop counter (92), and the loop counter (92) is connected with a Rückwärtszähler (94) and the internal data bus (90) is connected bidirectional with a batch pointer (102, a back jump-batch pointer (104, a mode register (106) and an order register (108), and and the internal data bus is connected with a memory control (118), thereby marked, the fact that the internal data bus (90) is connected bidirectional with a Y register (132) of a back jump-batch memory (134), with a X register (128) and with a program counter (130), the fact that the Y register (132), the X register (128) and the program counter deliver (130) source signals to an internal addressing bus (136), the fact that the internal addressing bus delivers input signals to the memory control (118) and to a Vorwärtszähler (144), the fact that the Vorwärtszähler (144) by the internal data bus (90) is connected, the fact that a separate direct memory access-CPU delivers (72) input signals to the memory control (118), namely everything in one single integrated circuit, and the fact that the memory control (118) shows an addressing bus and data bus (150) and a huge number of tax pipelines (152) to the connection with a RAM.

2. Microprocessor after claim 1 and the memory control (118) shows a Multiplex equipment (378, 382) between the CPU (70) and the addressing bus and data bus (150) and the Multiplex equipment (378, 382) is so connected and is configured that she delivers line addresses, fissure addresses and data over the addressing bus and data bus (150)

3. Microprocessor after claim 1 or 2 and the memory control (118) shows an equipment (370, 372, 384) to the call for orders for the CPU (70) on the addressing bus and data bus (150) and the equipment is so configured to the call for orders that she calls away several orders following on each other in one single memory cycle

4. Microprocessor require a memory access after claim 3, furthermore with an equipment (190, 192) which is connected with the equipment (370, 372, 384) to the call for orders to determine whether several orders, which have been called away by the equipment (370, 372, 384) to the call for orders and the equipment (370, 372, 384) calls away several orders to the call for orders, in addition, if to several orders require no access to the memory.

5. Microprocessor shows a fissure buffer for taking up to several orders after claim 3 or 4 and the microprocessor (310) are included and more dynamic RAM-memory (311) in one single integrated circuit (312) and the equipment (370, 372, 384) to the call for orders.

6. Microprocessor after one of the preceding claims and the microprocessor (50) shows an abbot branch circuit (410) and a driver's circuit (418) as well as an Exit release management (152) to the connection between the RAM-memory (150), the abbot branch circuit (410) and the driver's circuit (418) and the abbot branch circuit (410) is so configured that she delivers a return light if the exit-release management (150) reaches a precertain electric level recorder and and the microprocessor (50) is so configured that the driver's circuit (418) delivers a release signal on the Exit to release management (152) as a reaction to the return light

7. Microprocessor after one of the preceding claims, furthermore with a ring oscillator-system tact giver (430) at variable speed who is connected with the main CPU (70) and the main CPU and the ring oscillator-system tact giver (430) at variable speed are planned in one single integrated circuit.

8. Microprocessor after claim 7 and the memory control (118) shows an input interface and source interface (432) which is so connected that she exchanges coupling control signals, addresses and data with the main CPU (70) and the microprocessor shows, in addition, the second tact giver (434) who is independent of the ring oscillator-system tact giver (430) at variable speed and is connected with the input interface and source interface (432).

9. Microprocessor after one of the preceding claims and the first batch memory shows (74) following: the first huge number of the batch elements (456) which are configured as a buffer, the second huge number of the batch elements (458) which are configured as a RAM, and the first and second huge number are planned by batch elements and the CPU (70) in one single integrated circuit, as well as the third huge number of the batch elements (454) which are configured as a RAM outside by the only integrated circuit.

10. Microprocessor after the claim 9 which shows, in addition, the following: the first pointer (462 which is connected with the first huge number of batch elements (456), the second pointer which is connected with the second huge number of batch elements (458), and the third pointer which is connected with the third huge number of batch elements (454), and the CPU (70) is so connected that it takes positions from the first huge number of batch elements, and the first batch pointer (462 is connected with the second batch pointer to take the first huge number of positions from the second huge number of batch elements (458) if the first huge number of batch elements is empty on the basis of the withdrawal processes following on each other by the CPU, and the second batch pointer is connected with the third batch pointer to take the second huge number of positions from the third huge number of batch elements (454), if the second huge number of Infers from batch elements, and the first batch pointer (462 is connected with the second batch pointer to take the first huge number of positions from the second huge number of batch elements (458) if the first huge number of batch elements is empty on the basis of the withdrawal processes following on each other by the CPU, and the second batch pointer is connected with the third batch pointer to take the second huge number of positions from the third huge number of batch elements (454) if the second huge number of batch elements (458) is empty on the basis of the withdrawal processes following on each other by the CPU (70).