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Mosaic ImmunoEngineering is a nanotechnology-based immunotherapy company developing therapeutics and vaccines to positively impact the lives of patients and their families.
Message: Interest case in 2004, because it is similar our claims. Did Intel pay off ???
Interest case in 2004, because it is similar our claims. Did Intel pay off ???
I humbly suggest reading the original patent:
Apparatus and method for enhancing the performance of personal computers
Document Type and Number:
United States Patent 5450574
Abstract:
An accelerator board for use in replacing the microprocessor of a computer system board having a system clock. The accelerator board includes a high frequency oscillator which may be stopped and started under the influence of a clock enable signal. The clock enable signal is synchronized with the phase and logic state of the system clock, to form a clock select signal which serves to toggle a clock selector. When a system access is requested, clock enable stops the high frequency oscillator in a specific phase and logic state, and also toggles the clock selector to select the system clock as the clock speed for all accelerator board operations, giving a smooth transfer. When system access is no longer requested, the high frequency oscillator is restarted and is selected by the clock selector for all accelerator board operations. No time delay is encountered in switching from low to high speeds.
Title:
Apparatus and method for enhancing the performance of personal computers
Document Type and Number:
United States Patent 5506981
Abstract:
An accelerator board for use in replacing the microprocessor of a slow speed system board with a microprocessor operating at a higher clock speed. The clock signal of the accelerator board is derived from the clock signal of the system board by first deriving a sub-harmonic frequency which is a common denominator of both the system board and the accelerator board clock signal, and using the sub-harmonic signal to control a phase locked loop oscillator to provide the desired clock speed for the accelerator board. The arrangement provides a known phase relationship between the system clock signal and the accelerator board clock signal ( which facilitates data transfer between the system board and the accelerator board. The arrangement also provides a stable clock signal for the accelerator board in those instances where the clock speed of the system board may change for certain I/O operations of the system board.
This application is a continuation in part of application Ser. No. 08/037,875 filed Mar. 29, 1993
Be well
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