The SEAforth 40C18 is one of the IntellaSys Scalable Embedded Array
multicore processors. It has an array of 40 corSEAforth 40C18 Data Sheet
(Preliminary)es; each of the C18 cores is a complete computer, with its
own ROM, RAM, and inter-processor communication. Together they can
deliver up to 26 billion operations per second. The SEAforth 40C18 is a
perfect embedded computer solution for consumer applications that
demand high processing power and low power dissipation.
Each core is an 18-bit, stack-oriented machine designed waiting for data from a neighbor goes to sleep, dissipating less than one
microwatt. Likewise, a core sending data to a neighbor not ready to
receive it goes to sleep until that neighbor accepts it.
A wake up occurs almost instantly, upon the rising edge of the
synchronizing signal. With the wake up logic controlling power use,
there is no need for complex power control strategies. Power is
conserved as a natural consequence of good program design. External I/
O signals may also be used to wake up sleeping processors. The small
size and low power make the SEAforth 40C18 a good value both in terms
of MIPS per dollar and MIPS per milliwatt.
I/O ports on the SEAforth 40C18 are highly configurable With 40 cores to work with, designers can dedicate groups of them to
specific tasks such as FFT and DFT algorithms. The result is a tightlycoupled,
extremely versatile user-defined group of dedicated processors
assigned to specific tasks. Some can be doing highly compute-intensive
audio processing, while others handle wireless interfaces, external
memory, and user interface functions. And since each core has its own
ROM and RAM, there is less need to go to external memory.
Each core runs asynchronously, at the full native speed of the silicon.
During interprocessor communication, synchronization happens
automatically; the programmer does not have to create synchronization
methods. Adjacent cores communicate through dedicated ports. A core
because they
are controlled by firmware. The 4-wire SPI port, the 2-wire serial ports,
and the single-bit GPIO ports can be programmed to perform a large
variety of functions. With the available processing power, wireless
solutions become possible without the need for separate wireless chips.
Ports can be programmed to support I2C, I2S, asynchronous serial, or
synchronous serial ports. Serial ports can also be used to connect
multiple SEAforth 40C18s.
In addition to serial I/O, two nodes have two dedicated parallel I/O
ports. These can be used for parallel I/O, or when combined, can drive
an external memory device.
for maximum
execution speed and minimum power consumption. The instruction set
consists of 32 basic opcodes and each core uses a data stack for
manipulating parameters and a return stack for control flow nesting. Each
core has its own ROM (for the IntellaSys-supplied BIOS) and its own
RAM for user code and data. To reduce bottlenecks, each core’s code is
stored in its own memory.
At boot time, code is loaded into the appropriate core’s RAM. There are
several ways this can be done, but the simplest is from FLASH memory
through an SPI port. A single FLASH chip can load multiple SEAforth
40C18 chips that are interconnected.