Description of US2007271441

RELATED APPLICATIONS
[0001] This application is a divisional of co-pending U.S. patent application Ser. No. 09/051,263, filed Aug. 7, 1998, which claims priority to App. No. PCT/US96/16013, now Pub. No. WO 97/15001, filed Oct. 4, 1996, which claims priority to U.S. Provisional App. No. 60/005,408 filed Oct. 6, 1995, all of which are by the same inventors and incorporated in their entirety herein by reference.

INTRODUCTION
[0002] 1. Technical Field
[0003] This invention relates to an improved form of a simplified, reduced instruction set computer (RISC) microprocessor. More particularly, it relates to such a microprocessor implemented with a stack architecture.
[0004] 2. Background
[0005] Since the invention of the microprocessor described in the above related applications, all based on a common disclosure which is hereby incorporated by reference herein, improvements have been made in that microprocessor to enhance its performance and manufacturability. The following description discloses those improvements in the context of a presently preferred embodiment of that microprocessor.

SUMMARY OF THE INVENTION
[0006] In one aspect of the invention, a microprocessor system includes a microprocessing unit and an input-output processor (IOP). A global memory unit is coupled to the central processing unit and to the IOP. A means arbitrates access of the central processing unit and the IOP to the global memory unit. In one form, the global memory unit comprises a plurality of global registers.
[0007] In another aspect of the invention, a microprocessor system, has a microprocessing unit and an input-output processor (IOP). A memory interface unit selectively couples the central processing unit and the IOP to a system bus. A means grants the IOP access to the system bus at predetermined intervals.
[0008] In a further aspect of the invention, a microprocessor system has a microprocessing unit in which is included an arithmetic logic unit coupled to a stack cache. A means, coupled to the arithmetic logic unit and to the stack cache, determines the availability of stack cache resources by determining whether a value is included in at least one cell of the stack cache and whether at least one other cell of the stack cache is empty. A means, coupled to the means for determining the availability of the stack cache resources, selectively inhibits instruction execution by the arithmetic logic unit based on the availability of the stack cache resources.
[0009] In still another aspect of the invention, a microprocessor system has a microprocessing unit in which is included an arithmetic logic unit coupled to a stack cache. The stack cache is allocated at least a first portion of system memory. A means, coupled to the microprocessing unit and to the stack cache, executes a stack management trap when a stack pointer of the stack cache assumes an address within a boundary region of the first portion of the system memory. The stack management trap determines availability of at least one other portion of the system memory. A means, coupled to the means for executing the stack management trap, prevents another execution of the stack management trap until after the stack pointer has assumed an address within a predefined region of the first portion of the system not included within the boundary region.
[0010] In a still further aspect of the invention, a microprocessor system has a microprocessing unit and a memory interface unit coupling the microprocessing unit to system random access memory (RAM). The microprocessor system includes means, coupled to the memory interface unit, for converting logical row addresses provided by the microprocessing unit to physical row addresses of the system RAM so as to define virtual system memory using the system RAM.
[0011] In yet another aspect of the invention, a microprocessor system, includes a register unit. The register unit has at least one storage location containing a value to be interpreted as a memory address. A memory interface unit is coupled to the register unit. A memory bus is coupled to the memory interface unit. A system memory is coupled to the memory interface unit by the memory bus. The memory interface unit comprises transfer logic to increment the memory address and to generate a boundary detected signal when after a memory bus transaction to the system memory using the memory address, the memory address after incrementing has a value that is an even multiple of 2'', where n is a nonnegative integer.
[0012] In a still further aspect of the invention, a microprocessor system includes a central processing unit and a bit input register coupled to the central processing unit. The bit input register receives logical input over at least one bit line. The bit input register has a latch coupled to the at least one bit line, which initially samples the at least one bit line in order to determine a logic level thereof. A zero persistence control unit is coupled to the latch for storing the logic level in a register assigned to the at least one bit line. The logic level remains stored in the register until the zero persistence control unit is provided with a predefined signal by the central processing unit.
[0013] In another aspect of the invention, a microprocessor system, comprising a microprocessing unit, an input-output processor (IOP), and a memory interface unit selectively coupling said central processing unit and said IOP to a system bus, said IOP including program counter means for providing system address information to said memory interface unit.
[0014] In a further aspect of the invention, a microprocessor system includes a microprocessing unit having a stack cache. A system for effecting floating-point mathematical instructions includes an arithmetic logic unit means for performing floating-point operations upon values within cells of the stack cache. A means, coupled to the arithmetic logic unit means, generates floating point exceptions in response to performance of selected ones of the floating point operations. A mode register means, coupled to the arithmetic logic unit means and to the means for generating floating point exceptions, enables the microprocessing unit to execute predefined floating point routines in response to the floating point exceptions.

09/051,263 RISC MICROPROCESSOR ARCHITECTURE