Keeping in mind the benefits of the 336 which are as follows:

Accordingly, it is an object of this invention to provide a microprocessor with a reduced pin count and cost compared to conventional microprocessors.

It is another object of the invention to provide a high performance microprocessor that can be directly connected to DRAMs without sacrificing microprocessor speed.

It is a further object of the invention to provide a high performance microprocessor in which DMA does not require use of the main CPU during DMA requests and responses and which provides very rapid DMA response with predictable response times.

Some (probably not all) Problems I see with Ledzius 4691124

Not a free running clock, hence teaches away from the 336.

Processing of data is asynchronous to processor, thus teaching away from 336.

Compensation of process caused variations only dealt with clock generator and functional circuit 16. It is silent with respect to the processor.

Communication with the processor defeats asynchronous operation of functional circuit 16, hence teaches away form 336.

Processor is controlled by external clock, which teaches away from the 336.

The exact number and type of gates contained within each delay element are selected to provide specified delays, and hence the max frequency is predetermined by design, which teaches away from the 336.

Functional circuit 16 does not need to communicate with processor, hence limited in application, and thus teaches away from the 336.

The slowest propagation delay claims to define the true maximum speed of operation for functional circuit 16, but it is silent with respect to max speed of the processor.

Where’s the DRAM? How does this prior art teach the use of DRAM memory by the processor? What is the incentive to combine these prior arts? Comments/Corrections welcomed. Opty