New patent ??? FISH, Russell, H., III Publication Date: 16.08.2007 THREAD OPTIMIZED MULTIPROCESSOR ARCHITECTURE
posted on
Sep 09, 2007 06:30AM
Publication Number: |
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WO/2007/092528 |
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International Application No.: |
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PCT/US2007/003313 |
Publication Date: |
16.08.2007 |
International Filing Date: |
05.02.2007 |
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Int. Class.: |
G06F 9/30 (2006.01) |
Applicant: |
FISH, Russell, H., III [US/US]; 5400 Preston Oaks Road, Dallas, TX 75250 (US). |
Inventor: |
FISH, Russell, H., III [US/US]; 5400 Preston Oaks Road, Dallas, TX 75250 (US). |
Agent: |
UNDERWOOD, Steven, D.; MORGAN LEWIS, 1111 Pennsylvania Ave., NW, Washington, D.C. 20004 (US). |
Priority Data: |
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Title: |
THREAD OPTIMIZED MULTIPROCESSOR ARCHITECTURE
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Abstract: |
In one aspect, the invention comprises a system comprising: (a) a plurality of parallel processors on a single chip; and (b) computer memory located on the chip and accessible by each of the processors; wherein each of the processors is operable to process a de minimis instruction set, and wherein each of the processors comprises local caches dedicated to each of at least three specific registers in the processor. In another aspect, the invention comprises a system comprising: (a) a plurality of parallel processors on a single chip; and (b) computer memory located on the chip and accessible by each of the processors, wherein each of the processors is operable to process an instruction set optimized for thread-level parallel processing.
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http://www.wipo.int/pctdb/en/fetch.j... +