I'd say I'm more cautious than concerned.

Average dynamic memory read cycle times where significantly slower than CPU cycle times even when we were using LSI devices. CPUs and Memory where built of many parts on seperate PCBAs back then. There was still the same "slow memory cycle" concern that was being addressed by many companies.

I don't think the integration of all these Memory and CPU parts into a single chip is a factor in this patent's claims. The patent seems to be independent of the level of integration of any design. A two edged sword.