The foundation of the PTSC patent (MMP Portfolio) is US patent 336, Clocking CPU and I/O Separately . According to TPL, use of US`336 is prevalent across most microprocessors from low speed microcontrollers to sophisticated systems on chips.

Is the cell processor architecture changed from clocking CPU and I/O seperately? probable NOT.

Cell processor info from http://www.blachford.info/computer/Cell/Cell1_v2.html

Memory controller and I/O

Cell contains a dual channel next-generation Rambus XIO macro which interfaces to Rambus XDR memory. The memory interface controller (MIC) is separate from the XIO macro and is designed by IBM. The XIO-XDR link runs at 3.2 Gbit/s per pin. Two 32 bit channels can provide a theoretical maximum of 25.6 GB/s.

The system interface used in Cell, also a Rambus design, is known as FlexIO. The FlexIO interface is organized into 12 ``lanes,`` each lane being a unidirectional 8-bit wide point-to-point path. Five 8-bit wide point-to-point path are inbound lanes to Cell, while the remaining seven are outbound. This provides a theoretical peak bandwidth of 62.4 GB/s (36.4 GB/s outbound, 26 GB/s inbound) at 2.6 GHz. The FlexIO interface can be clocked independently, typ. at 3.2 GHz. 4 inbound + 4 outbound lanes are supporting memory coherency.

A picture worths thousands of words:

According to TPL website, they mentioned one of the MMP - US 148 has implementations on Cell:

http://www.alliacense.com/licensing/mmpBackground.html

US`148: On-Chip Oscillator and Embedded Memory Shares the on-chip oscillator feature with US`336, in addition to memory covering more than majority of chip. Also includes claims pertaining to multiple CPU, array or cell implementations . The vast majority of the SoC and flash microcontroller products are affected.

For more background info on US Patent 336:

http://www.investorshub.com/boards/read_msg.asp?message_id=6576917

Excerpts from PTSC`s U.S. Patent 5,809,336 1995 --``A high performance, low cost microprocessor system having a variable speed system clock is disclosed herein. The microprocessor system includes an integrated circuit having a central processing unit and a ring oscillator variable speed system clock for clocking the microprocessor. The central processing unit and ring oscillator variable speed system clock each include a plurality of electronic devices of like type, which allows the central processing unit to operate at a variable processing frequency dependent upon a variable speed of the ring oscillator variable speed system clock. The microprocessor system may also include an input/output interface connected to exchange coupling control signals, address and data with the central processing unit. The input/output interface is independently clocked by a second clock connected thereto.`` & ``Most microprocessors derive all system timing from a single clock. The disadvantage is that different parts of the system can slow all operations. The microprocessor 50 provides a dual-clock scheme as shown in FIG. 17, with the CPU 70 operating a synchronously to I/O interface 432 forming part of memory controller 118 (FIG. 2) and the I/O interface 432 operating synchronously with the external world of memory and I/O devices. The CPU 70 executes at the fastest speed possible using the adaptive ring counter clock 430. Speed may vary by a factor of four depending upon temperature, voltage, and process. The external world must be synchronized to the microprocessor 50 for operations such as video display updating and disc drive reading and writing. This synchronization is performed by the I/O interface 432, speed of which is controlled by a conventional crystal clock